The invention relates to CMOS amplifiers and low-impedance output stages therefor, and especially to low-impedance output stages that maintain acceptable levels of quiescent bias current in the output transistors thereof over usual variations of operating temperature, supply voltages, and integrated circuit processing parameters.
An ideal integrated circuit CMOS amplifier would have an output stage that provides very low output impedance, large output voltage swings between the positive and negative power supply voltage levels, a linear output signal, and low distortion. A selected DC or quiescent bias current in the output transistors of the output stage should be essentially constant for acceptable ranges of power supply voltage, mismatches between transistors, resistors and other components of the circuit, and various integrated circuit processing parameters.
Providing CMOS amplifier circuits with low output impedance and constant quiescent current (i.e., no load current) over an acceptable range of processing parameters and circuit operating conditions has been particularly challenging to those skilled in the art. It is known to use "quasi-devices", which include an error amplifier with a large output MOSFET of one channel type, e.g., N-channel, to "mimic" the behavior of a MOSFET of the opposite channel type (P-channel in this case). Such "quasi-devices" often are used in source-follower configurations as shown in FIG. 1A hereof. Output stages comprised of quasi-devices have low output impedance, as do source followers, and have the further advantage of larger output voltage swings than source followers.
In U.S. Pat. No. 4,480,230 (Brehmer et al.), additional circuitry is added to a class AB output stage to sense when large quiescent currents are flowing in the output MOSFETs to provide feedback which is used to attenuate the quiescent (no-load) current in the output MOSFETs. U.S. Pat. No. 5,162,752 (Khorramabadi) discloses use of class B output MOSFETs and class AB output MOSFETs connected in parallel and driven from separate error amplifiers. However, both the Brehmer et al. and Khorramabadi circuits are complex, and neither solves the problem of substantial variation in the amount of quiescent current that flows through the output MOSFETs as a function of typical variations in temperature, power supply voltage, and integrated circuit process parameters.
Referring to FIG. 1, the portion 2 of the illustrated bias circuit that includes resistor R1 and MOSFETs M1-M6 constitutes a prior art bias circuit which operates so as to keep MOSFET M1 at the edge of strong inversion, i.e., just at the edge of being turned "on". That bias circuit 2 is commonly used to provide bias voltage on conductors 12 and 13 to drive current mirror output transistors such as M9 and M10 in FIG. 1. Such current mirror output transistors function as a constant current source for a differential amplifier stage 3. However, the prior art portion 2 of the circuit 1 of FIG. 1 provides no guidance to solving the above mentioned problem of maintaining the quiescent bias current in the output transistors of a CMOS amplifier constant over typical ranges of power supply voltage, temperature, and CMOS processing parameters. Although some of the above-mentioned variations in integrated circuit process parameters can be compensated for by laser trimming of thin film resistors, it is desirable to avoid laser trimming, because it is a very costly process.
Consequently, there still is an unmet need for an improved low-impedance CMOS output stage which can provide large output voltage swings between positive and negative power supply voltages and which has substantially constant quiescent current in the output MOSFETS, without adding undue complexity to the circuitry of the output stage, and without incurring the costs associated with laser trimming of thin film resistors or the like.